A data processing system of the above-described general type is proposed in U.S. Pat. No. 5,414,858. In the computer system described in that patent the latency associated with interrupt processing is said to be relatively high since the interrupt signals initiate operating system routines that are relatively time consuming. On the other hand, the latency associated with polling is said to be relatively low, since the frequency of the polling can be made relatively fast.
In consequence, the patent proposes dynamically switching from an interrupt driven mode to a polling mode in order to reduce latency.
However, the power of modern processors means that the latency associated with interrupt driven processing is sufficiently low so as not to be significant for some applications. Nevertheless, even in powerfull modern computer systems, interrupt processing still involves a performance overhead for the computer, for example since data associated with the task or tasks the computer is performing when it receives the interrupt need to be saved and then restored once the interrupt routine has terminated.
The problem with the approach proposed in U.S. Pat. No. 5,414,858 is that, in at least some applications, the use of fast polling can also use significant processor resources and therefore the dynamic switching approach proposed would not necessarily provide any improvement in overall efficiency.
The object of this invention is to provide an improved technique for managing the servicing of peripheral devices in computer systems and which mitigates the above described drawback of the prior art.